MAX11647EUA+T【PDF 17/22 页】IC ADC 10BIT I2C 94.4KSPS 8UMAX

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Sheet目录2008

13页 14页 15页 16页 [17页]18页 19页 20页 21页

MAX11646/MAX11647

Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs

in Ultra-Tiny 1.9mm x 2.2mm Package

_______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646),

fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming

notation.) (Note 1)

TIMING CHARACTERISTICS (Figure 1)

(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646),

fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming

notation.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIREMENTS

Power-Supply Rejection Ratio

PSRR

Full-scale input (Note 10)

±0.01

±0.5

LSB/V

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS FOR FAST MODE

Serial-Clock Frequency

fSCL

400

kHz

Bus Free Time Between a

STOP (P) and a

START (S) Condition

tBUF

1.3

μs

Hold Time for a START (S)

Condition

tHD:STA

0.6

μs

Low Period of the SCL Clock

tLOW

1.3

μs

High Period of the SCL Clock

tHIGH

0.6

μs

Setup Time for a REPEATED

START Condition (Sr)

tSU:STA

0.6

μs

Data Hold Time

tHD:DAT

(Note 11)

900

Data Setup Time

tSU:DAT

100

Rise Time of Both SDA and SCL

Signals, Receiving

Measured from 0.3VDD to 0.7VDD

20 +

0.1CB

300

Fall Time of SDA Transmitting

Measured from 0.3VDD to 0.7VDD (Note 12)

20 +

0.1CB

300

Setup Time for a STOP (P)

Condition

tSU:STO

0.6

μs

Capacitive Load for Each Bus

400

Pulse Width of Spike

tSP

TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 13)

Serial-Clock Frequency

fSCLH

(Note 14)

1.7

MHz

Hold Time, REPEATED START

Condition (Sr)